ㆍ▷ COM Express Basic Size Type 6 Module with 11th Gen Intel® Core™, Intel® Xeon® W and Intel® Celeron® 6000 Processors (Tiger Lake-H)
ㆍ▷ AI inference (AVX512 VNNI + Intel® UHD GFX + OpenVINO™ toolkit)
ㆍ▷ Up to 128GB DDR4 SO-DIMM, non-ECC and ECC
ㆍ▷ 3x DDI channels, 1x LVDS (opt. 4 lanes eDP), opt. VGA, up to 4 independent displays, 8K capable
Features
▷ New Gen Intel® Processors, up to 8 cores, integrated Intel® Iris®
Xe graphics
▷ AI inference (AVX512 VNNI + Iris Xe GFX)
▷ Up to 128GB DDR4 SO-DIMM, non-ECC and ECC
▷ 3x DDI channels, 1x LVDS (opt. 4 lanes eDP), opt. VGA,
up to 4 independent displays
▷ PCIe x16 Gen4, 2.5GbE (TSN, build option)
▷ Extreme Rugged operating temperature: -40°C to +85°C
(build option, selected SKUs
Specification & Introduction
▷ CPU
New Gen Intel® Core™ and Celeron® Processors - Mobile 10nm++ process
Xeon®, 24MB, 45W (35W cTDP), 8C
Core™ i7, 24MB, 45W (35W cTDP), 8C
Core™ i5, 12MB, 45W (35W cTDP), 6C
Core™ i3, 8MB, 45W (35W cTDP), 4C
Celeron®, 8MB, 35W, 2C
Supports: Intel® VT, Intel® VT-d, Intel® TXT, Intel® SSE4.2, Intel® HT Technology,
Intel® 64 Architecture, Execute Disable Bit, Intel® Turbo Boost Technology 2.0,
Intel® AVX-512, Intel® AVX2, Intel® AES-NI VT, Intel® VT-d, Intel® TXT, Intel®
SSE4.2, Intel® HT Technology, Intel® 64 Architecture, Execute Disable Bit,
Intel® Turbo Boost Technology 2.0, Intel® AVX-512, Intel® AVX2, Intel® AES-NI,
PCLMULQDQ Instruction, Intel® Secure Key and Intel® TSX-NI.
▷ Memory
Dual channel up to 3200 MT/s non-ECC/ECC DDR4 memory up to 128GB in
four SODIMM sockets
Two SO-DIMM on top side, two SO-DIMM on bottom side (3 or 4 socket
versions by build option)
ECC dependent on CPU/chipset combination (TBC)
▷ Embedded BIOS
AMI UEFI with CMOS backup in 32 or 16MB (TBC) SPI BIOS (dual BIOS by
build option)
▷ Cache
24MB for Xeon®, 24MB for Core™ i7, 12MB for Core™ i5, 8MB for Core™ i3,
8MB for Celeron®
▷ Chipset
RMXXXE Chipset (supports ECC, with selected CPU SKUs)
QMXXXE Chipset
HWXXXE Chipset
▷ Expansion Busses
PCIe x16 Gen4 (CD): Lanes 15-31 (configurable to one x16, two x8, one x8 + two x4)
6 PCIe x1 Gen3 (AB): Lanes 0/1/2/3 (configurable to x1, x2, x4) and Lanes 4/5
(x2, x1)
2 PCIe x1 Gen3 (CD): Lanes 6/7 (configurable to x2, x1)
LPC bus (through an ESPI to LPC bridge IC), SMBus (system) , I2C (user)
▷ SEMA Board Controller
Supports: Voltage/current monitoring, power sequence debug support, AT/
ATX mode control, logistics and forensic information, flat panel control,
general purpose I2C, watchdog timer, fan control and failsafe BIOS (dual
BIOS by build option)
▷ Debug Headers
30-pin multipurpose flat cable connector for use with DB-30 x86 debug
module providing BIOS POST code LED, EC access, SPI BIOS flashing, power
testpoints, debug LEDs
Ordering Information